50 lines
1.6 KiB
Makefile
50 lines
1.6 KiB
Makefile
# Thanks to Job Vranish (https://spin.atomicobject.com/2016/08/26/makefile-c-projects/)
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TARGET_EXEC := final_program
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BUILD_DIR := ./build
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SRC_DIRS := ./src ./includes
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RESOURCE_DIRS := ./resources
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CC := gcc
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ld := gcc
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LDFLAGS = -lm
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BASEFLAGS = -std=c17 -g -O3 -D_POSIX_C_SOURCE=199309L -Wall -Wextra -Wconversion -Wduplicated-branches -Wduplicated-cond -Wlogical-op -Wnull-dereference -Wdouble-promotion -Wshadow -Wformat=2
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CFLAGS = $(BASEFLAGS) -Wjump-misses-init
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# Find all the C and C++ files we want to compile
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# Note the single quotes around the * expressions. The shell will incorrectly expand these otherwise, but we want to send the * directly to the find command.
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SRCS := $(shell find $(SRC_DIRS) -name '*.c')
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# Prepends BUILD_DIR and appends .o to every src file
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# As an example, ./your_dir/hello.cpp turns into ./build/./your_dir/hello.cpp.o
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OBJS := $(SRCS:%=$(BUILD_DIR)/%.o)
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# String substitution (suffix version without %).
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# As an example, ./build/hello.cpp.o turns into ./build/hello.cpp.d
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DEPS := $(OBJS:.o=.d)
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# Every folder in ./src will need to be passed to GCC so that it can find header files
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INC_DIRS := $(shell find $(SRC_DIRS) -type d)
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# Add a prefix to INC_DIRS. So moduleA would become -ImoduleA. GCC understands this -I flag
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INC_FLAGS := $(addprefix -I,$(INC_DIRS))
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# The final build step.
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$(BUILD_DIR)/$(TARGET_EXEC): $(OBJS)
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cp -r resources/. build
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$(ld) $(OBJS) -o $@ $(LDFLAGS)
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# Build step for C source
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$(BUILD_DIR)/%.c.o: %.c
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mkdir -p $(dir $@)
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$(CC) $(CPPFLAGS) $(CFLAGS) -c $< -o $@
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.PHONY: clean
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clean:
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rm -r $(BUILD_DIR)
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